library IEEE;
use ieee.std_logic_1164.all;

package package_micro_simple is
	component alu is
	port(a,b: in	std_logic_vector (7 downto 0);
		 sel : in	std_logic_vector (3 downto 0);
 		 cin : in   std_logic;
		 y	 : out	std_logic_vector (7 downto 0)
		 );
	end component;
	
	component reg_8 is
	port(a		  : in	std_logic_vector (7 downto 0);
		 clk, rst, inc, load : in   std_logic;
		 z	 	  : out	std_logic_vector (7 downto 0)
		 );
	end component;
	
	component micro_codigo is
	PORT
	(
		ir					: IN	STD_LOGIC_VECTOR(7 downto 0);
		tc					: IN	STD_LOGIC_VECTOR(7 downto 0);
		microbus			: OUT	STD_LOGIC_VECTOR(15 downto 0)
	);
	end component;
	
	component mux is
	port
	(
		a,b		: IN	STD_LOGIC_VECTOR(7 downto 0);
		sel		: IN 	STD_LOGIC;
		z		: OUT	STD_LOGIC_VECTOR(7 downto 0)
	);
	end component;
end package_micro_simple;
